1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device and a manufacturing method thereof, and in particular, to a nonvolatile semiconductor storage device and a manufacturing method thereof which can reduce a capacity between floating electrodes and which can improve reliability of the device.
2. Description of the Related Art
Conventionally, a nonvolatile semiconductor storage device is used for a storage LSI or the like. FIG. 5 and FIG. 6 are cross-sectional views showing a manufacturing process of a nonvolatile semiconductor storage device. An element isolation forming process and a floating electrode forming process are included in the manufacturing process of the nonvolatile semiconductor storage device.
FIGS. 5A and 5B are cross-sectional views showing the element isolation forming process for forming element isolation portions. First, a first silicon oxide film 2, a first polycrystalline silicon film 3, a silicon nitride film 4, and a second silicon oxide film 5 are formed on the silicon substrate 1. Further, photo resist (unillustrated) is processed so as to be a desired pattern by photolithography, and the silicon nitride film 4 and the second silicon oxide film 5 are etched by an RIE (Reactive ion etching) method by using the photo resist as a mask.
Next, the silicon substrate 1 is exposed in O2 plasma, and the photo resist is eliminated. Further, the polycrystalline silicon film 3, the first silicon oxide film 2, and the silicon substrate 1 are etching-processed by using the second silicon oxide film 5 as a mask, and as shown in FIG. 5A, trenches 1a are formed in the silicon substrate 1.
Next, a third silicon oxide film 6 of several nm is formed by being heated in an O2 atmosphere, and thereafter, fourth silicon oxide films 7 are filled by an HDP (high density plasma)—CVD (chemical vapor deposition) method in the grooves 1a in the silicon substrate 1. Further, the fourth silicon oxide films 7 are flattened by a CMP (chemical mechanical polish) method and are heated in a nitrogen atmosphere. Next, after the device is immersed in an NHF4 solution, the fourth silicon nitride film 4 is removed by phosphoric acid to 150° C. as shown in FIG. 5B. The element isolation process for forming STI (isolation) is described up to the above description.
Next, the floating electrode forming process is carried out. As shown in FIG. 6A, the second polycrystalline silicon film 8 to which phosphorus are added and the fifth silicon oxide film 9 are formed by a low pressure CVD method, and photo resist R is processed so as to be a desired pattern by photolithography. The fifth silicon oxide film 9 is etching-processed by the RIE method by using the photo resist R as a mask material. Further, the silicon substrate 1 is exposed in O2 plasma, and the photo resist R is eliminated.
Next, as shown in FIG. 6B, the sixth silicon oxide film 10 is formed by the low pressure CVD method. The fifth silicon oxide film 9 and the six silicon oxide film 10 are etching-processed by using the sixth silicon oxide film 10 as a mask material. Next, by using the fifth silicon oxide film 9 and the six silicon oxide film 10 as mask materials, as shown in FIG. 6C, the second polycrystalline silicon 8 is etched by the RIE method.
Next, the silicon substrate 1, is immersed in a weak NHF4 solution in order to remove the fifth silicon oxide film 9 and the sixth silicon oxide film 10, an ONO film (SiO2—SiN, —SiO2 film) 11 is formed by the low pressure CVD method, and heat treatment is applied to the device in an oxide atmosphere. Next, as shown in FIG. 6D, a third polycrystalline silicon film 12 which will be an insulating layer is formed by the low pressure CVD method.
Note that, with respect to the cross-section of a memory cell array, there are memory cell arrays in which the width between adjacent floating electrodes is greater at the side away from the substrate than at the substrate side. However, there is no particular explanation as to the reason why such a structure/configuration is used.
In the method for manufacturing the above-described nonvolatile semiconductor storage device, there has been the following problem. Namely, in the floating electrode forming process, the process of isolating the floating electrode must be carried out on the element isolating region. Therefore, the width of floating electrode trench is limited by the width of the element isolating region and the alignment offset amount of the PEP (Photo Etching Process), and the interval between the floating electrodes cannot be made sufficiently wide. If the interval between the floating electrodes is narrow, fluctuations in the threshold voltage arise due to the capacitive coupling between the floating electrodes, which significantly affects the reliability of the device.
FIG. 7 through FIG. 9 are explanatory diagrams showing the principles of fluctuations in threshold voltage. Namely, as shown in FIGS. 7A through 7C, the nonvolatile semiconductor storage device carries out storage by injecting electric charge into a floating electrode FG by FN tunnel current. At this time, in the case of 1-bit cell NAND flash memory, as shown in FIG. 7B, because the electric charge corresponds to “0” or “1”, Vths are apart from each other. On the other hand, for example, in the case of a multilevel cell NAND flash memory, as shown in FIG. 7C, because the electric charges are “01”, “00”, “10”, and “11”, and Vths are close to one another.
Therefore, as shown in FIGS. 8A and 8B, writings are successively carried out into the floating electrodes, and in the case of maintaining electric charge, when a capacity between the floating electrodes becomes large between the floating electrodes adjacent to one another, there may be a case where fluctuations in electric potential arise by being affected by electric charge of the adjacent floating electrode.
As shown in FIG. 8C, when the capacity between the floating electrodes becomes large, this is a cause of a threshold voltage distribution M1 denoting “10”, for example, to shift to the threshold voltage distribution M2, and of the interval with an adjacent threshold voltage distribution denoting “00” to be narrowed from m1 to m2, and of the reliability of the device deteriorating.
FIG. 9 is an explanatory diagram showing an electric potential shift ΔVfg accompanying interference between the floating electrodes. Namely, the capacity between the floating electrodes is calculated on the basis of formula (1) by the adjacent capacities between the floating electrodes Cfgx, Cfgxy, Cfgy, and the capacities with the respective members Ctun, Cono.
                    Namely        ,                                  ⁢                                                                              Δ                  ⁢                                                                          ⁢                                      V                    fg                                                  =                                ⁢                                                      {                                                                                            (                                                                                    Δ                              ⁢                                                                                                                          ⁢                              V1                                                        +                                                          Δ                              ⁢                                                                                                                          ⁢                              V2                                                                                )                                                ⁢                                                  C                          fgx                                                                    +                                              Δ                        ⁢                                                                                                  ⁢                                                  V4C                          fgy                                                                    +                                                                        (                                                                                    Δ                              ⁢                                                                                                                          ⁢                              V3                                                        +                                                          Δ                              ⁢                                                                                                                          ⁢                              V5                                                                                )                                                ⁢                                                  C                          fgxy                                                                                      }                                    /                                                                                                                        ⁢                                  (                                                            C                      tun                                        +                                          C                      ono                                        +                                          2                      ⁢                                              C                        fgx                                                              +                                          2                      ⁢                                              C                        fgy                                                              +                                          4                      ⁢                                              C                        fgxy                                                                              )                                                                                        (        1        )            